The FinFET structure is used for advanced micro-electronic devices. An array of fins is generally formed by lithography and other material processing techniques, e.g., sidewall image transfer (SIT). A known approach for forming FinFET fins is depicted in FIGS. 1A and 1B. Adverting to FIG. 1A, a plurality of bulk silicon (Si) fins 101, i.e., fins that are formed directly from the Si substrate 103 and are contiguous to it, are formed by an etch process that digs into the silicon. A hard mask layer 105, e.g., made of silicon nitride (SiN), is formed on top of each of the plurality of bulk Si fins 101 and used as an etch stop during the fin formation process. An oxide layer 107, e.g., a high aspect ratio process (HARP) oxide, is then used to fill up the etched volume to electrically isolate the plurality of bulk Si fins 101. Next, the oxide layer 107 is planarized, e.g., by chemical mechanical polishing (CMP), down to the plurality of bulk Si fins 101, removing the hard mask layer 105, as depicted in FIG. 1B. Consequently, the resulting device may have the problem of dishing between the plurality of bulk Si fins 101 (not shown for illustrative convenience). In the final transistor device, current runs through the plurality of bulk Si fins 101. Electronic performance is improved if the carrier mobility in the bulk Si fins 101 is increased. Mobility can by modulated by the strain in the bulk Si fins 101. Baseline processes can generate stress in fins; however, not in the direction advantageous for a p-type FET (pFET).
A need therefore exists for methodology enabling increased mobility in FinFET structures with minimal disruption of the typical process flow and the resulting device.